Important Dates

  • Paper Submission Deadline :
  • 15 March, 2012
  • Paper Status Notification:
  • April 20, 2012
  • Camera-ready Due:
  • May 01, 2012
  • Conference:
  • July 13 ~ 15, 2012

Registered Papers

14
A comparitive study and analysis of Short channel effects in 180nm and new 45nm transistors
Kiran Agarwal Gupta 1, Dinesh K Anvekar 2, V.Venkateswarlu 3, 1 Visvesvaraya Technology
University, 2 Innovations & Six Sigma Specialist Honeywell Technology Solutions Lab, 3 UTL Technolgies Ltd,Bangalore,India
16
Reconfigurable RNS FIR filter Using Higher Radix Multiplier
Britto Pari. J and Joy Vasantha Rani.S.P., Anna university, Chennai
55
Design of Efficient Reversible Multiplier
Rangaraju H G1, Aakash Babu Suresh2, Muralidhara K N3, 1 Government Engineering College,India,
2 Robert Bosch Engineering and Business Solutions Limited, India, 3 P E S College of Engineering, India
64
CAD for Delay optimization of Symmetrical FPGA Architecture through Hybrid LUTs/PLAs
Sunil Kr. Singh1, R. K. Singh 1, M. P. S. Bhatia2, Saurabh P. Singh2, 1 Uttarakhand Technical University,India, 2 Netaji Subhash Institute of Technology (NSIT),India
100
Analysis on Impact of Behavioral Modeling in Performance of Synthesis Process
R.Uma and P. Dhavachelvan, School of Engineering, Pondicherry University, India
112
A VLSI Architecture For Wavelet Based Image Compression
Jayaraj U Kidav1, Ajeesh.P.A2, Drisya Vasudev2, Deepak.V.S2, Aiswarya menon2, 1DOEACC CENTRE,India and 2Vidya Academy Of Science And Technology,India
119
CMOS 8-BIT CURRENT-STEERING DIGITAL RANDOM RETURN TO ZERO DAC
Piyush K. Mathurkar and Madan B. Mali, University of Pune, Pune, India
127
Design of a Novel Reversible Multiplier and Reversible Subtractor
A.V. AnanthaLakshmi, G.F. Sudha,Pondicherry Engineering College,India
133
Operator Scheduling Revisited : A Multi-Objective Perspective for Fine-Grained DVS Architecture
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal, Indian Institute of Technology Kharagpur,India
139
A Scheme For Improving Bit Efficiency For Residue Number System
Chaitali Biswas Dutta1, Partha Garai2, Amitabha Sinha3, 1GIMT, Guwahati, India, 2Indian Statistical Institute, Kolkata and 3West Bengal University of Technology, India
144
Obstacle Aware RMST Generation Using Non-Manhattan Routing for 3D ICs
Prasun Ghosal1, Arindam Das2 and Satrajit Das2, 1Bengal Engineering and Science University,India and 2Purabi Das School of Information Technology,India
151
A Novel Routing Algorithm for On-chip Communication in NoC on Diametrical 2D Mesh Interconnection Architecture
Prasun Ghosal and Tuhin Subhra Das, Bengal Engineering and Science University,India
159
Reduction of crosstalk noise and delay in VLSI interconnects
Shikha Singh and Vemu Sulochana Verma, Centre for Development of Advanced Computing, Mohali, Punjab, India
160
Low Power Design Analysis of PLL Components in submicron Technology
Kanika Garg and Vemu Sulochana Verma, Centre for Development of Advanced Computing, Mohali, Punjab, India
178
A New Class of Obstacle Aware Steiner Routing in 3D Integrated Circuits
Prasun Ghosal, Satrajit Das, and Arindam Das, Bengal Engineering and Science University,India