Accepted Papers            Program Schedule


01 - Development of Controllability Observability Aided Combinational ATPG with Fault Reduction
          Vaishali Dhare and Usha Mehta, Nirma University - Ahmedabad, India

10 - Implementation of ADPLL with 0.6µm CMOS process for SOC Applications
           V. Leela Rani, V. Suma Latha, G.T. Rao and D.S. Murty, GVPCOE - Visakhapatnam, India

11 - Fault Diagnosis of Analog Circuits utilizing Reconfigurable Computing System
           Poonguzhali P and N. Sarat Chandra Babu, Centre for Development of Advanced Computing – Hyderabad, India

13 - A Low Voltage high performance OTA in 0.18 micron with High Linearity
           Nikhil Raj 1, Ranitesh Gupta 1 and Vikram Chopra 2, 1 National Institute of Technology – Haryana, India and            2 Thapar University – Punjab, India