Accepted Papers            

 

14
Design and Minimization of Reversible Programmable Logic Arrays
Sajib Kumar Mitra1, Lafifa Jamal1, Md. Abdul Mottalib2 and Hafiz and Md. Hasan Babu1, 1University of Dhaka,Bangladesh and 2Islamic University of Technology, Bangladesh
25
Efficient Design for Fault Tolerant Improved Rail Check for Online Testability
Sajib Kumar Mitra and Ahsan Raja Chowdhury, University of Dhaka, Bangladesh
44
Decimal Floating Point Multiplier using Double Digit Decimal Multiplication
Rekha K. James1, K. Poulose Jacob1 and Sreela Sasi2, 1Cochin University of Science and Technology, India and 2Gannon University, USA
47
Low power and high performance 4-bit register using MTCMOS conditional discharge flip flop
M. Harinath Reddy, M. Malathi, SRM University, India
52
Design of Low Power Column Bypass Multiplier using FPGA
Tushar V. More and R.V.Kshirsagar, Priyadarshini College of Engineering, India
64
A Comparative Analysis and Design of Low Energy Flip-Flops
65
Power and Crosstalk Reduction Using Bus Encoding Technique for RLC Model VLSI Interconnect
Deepika Agarwal, B.K.Kaushik and G.Nagendra Babu, Indian Institute of Technology-Roorkee, India
67
New Low Power and High Performance Full Adder
K.Venkateswara Rao1, Deepa Sinha and Kumari Deepmala, FET-MITS Lakshmangarh, India
68
New Efficient Design for AND Function on the Transistor Level
Kumari Deepmala and Deepa Sinha, FET-MITS Lakshmangarh, India
69
Novel Bus Encoding Scheme for RC Coupled VLSI Interconnects
S.K.Verma1 and B.K.Kaushik2, 1G.B. Pant Engineering College, India and 2Indian Institute of Technology-Roorkee, India
70
Propagation Delay Deviation Due to Process Induced Driver Width Variation
K.G. Verma1, B.K.Kaushik2, and R.Singh1, 1Shobhit University, India and 2Indian Institute of Technology-Roorkee, India
71
Performance Driven VLSI Floorplanning with B*Tree Representation Using Differential Evolutionary Algorithm
Gracia Nirmala Rani.D and Rajaram.S, Thiagarajar College of Engineering, India
72
Power reduction techniques applied to different technologies
Himani Mittal ,Dinesh Chandra and Sampath kumar, J.S.S.Academy of Technical Education, India
73
A BITCAM based Virus-Detection unit in Mobile Processors
H.Maheshkumar, S.M.Ramesh, Bannari Amman Institute of Technology, India
75
New Technique for LeakageCurrent Reduction in SRAM Cell Architecture
SRINIVASA RAO, S.RAGHAVENDRA, B.S.N.S.P. KUMAR and V.MALLESWARA RAO, GITAM University, India
81
Effect of Temperature and Gate Stack on the Linearity and Analog Performance of Double Gate Tunnel FET
Rakhi Narang1, Manoj Saxena2, R.S.Gupta3 and Mridula Gupta1, 1University of Delhi, India, 2Deen Dayal Upadhyaya College, India and 3Maharaja Agrasen Institute Of Technology, India
82
Channel Material Engineered Nanoscale Cylindrical Surrounding Gate MOSFET With Interface Fixed Charges
Rajni Gautam1, Manoj Saxena2, R.S.Gupta3 and Mridula Gupta1, 1University of Delhi, India, 2Deen Dayal Upadhyaya College, India and Maharaja Agrasen Institute Of Technology, India
84
Investigation of Performance Amelioration of FD-SOI MOSFET Using High-K Gate Spacer
Deepesh Ranka, Ashwani K. Rana , Rakesh Kumar Yadav andKamalesh Yadav, National Institute of Technology - Hamirpur, India
94
FPGA Implementation of Braun's Multiplier Using Spartan-3E, Virtex 4, Virtex-5 and Virtex-6.
Anitha R. and Bagyaveereswaran V.
96
Low Power High Throughput Differential Current Mode Signaling Technique for Global VLSI Interconnect
Sujeet Kumar , R.B. Deshmukh and R.M. Patrikar, VNIT - Nagpur, India
97
Inductive Degenerated CS-LNA for Wireless Application
Kapil Soni and R.M.Patrikar, VNIT, India
101
Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic
G.Jyoshna, P.Murali Krishna and B.Doss, JNT University, India
103
Design of Clock gated State Look-Ahead Logic based Digital CMOS Parallel Counter
K.Ramesh, Avinash Venigalla and Deepak Kumar Pandey, SRM University, India
106
Design of Adder and Multiplier using Quantum dot cellular automata based on Nanotechnology
DEEPAK KUMAR PANDEY1, NEELABH TIWARI1 and YOGITA PANT2, 1SRM UNIVERSITY, India and 2UNIVERSITY OF - LUCKNOW, India
115
0.5V CMOS Digital Integrated Circuits for Portable Systems
Alpesh Goyal , Animesh Sharma, Gaurav Gupta and Vishal Tripathi, International Institute of Information Technology, India
116
Wireless Sensor Based Security System With ucos-Ii Ported Arm
Ranjani R, Salmankhan.A and Pradeepa.M, Park College of Engineering and Technology, India
119
Delay and Transient Response Modelling of On-Chip RLCG Interconnect Using Two-port Network Functions
Madhumanti Datta, Susmita Sahoo and Rajib Kar, National Institute of Technology, India
120
Low Power VLSI Circuit Implementation using Mixed Static CMOS and Domino logic with Delay Elements
M.Sunil K Reddy, Rajib Kar, National Institute of Technology, Durgapur, India
122
A novel approach towards BDD generation and CNF conversion for half adder
Deepak Kumar Verma and Pankaj Srivastava, Indian Institute of Information Technology and Management, India
124
A Novel Method for Delay Analysis of CMOS Inverter with RLC Interconnect Load
Madhumanti Datta, Susmita Sahoo and Rajib Kar, National Institute of Technology, India
127
Optimization of Traffic Flow through Signalized Intersections using PSO
Parag Hirulkar, Preeti Bajaj and Rahul Deshpande, G. H. Raisoni College of Engg, India
128
A Design Approach for Driver's Vigilance and Monitoring system
Rushikesh Bankar, Preeti Bajaj and Rahul Deshpande, G. H. Raisoni College of Engineering, India
131
Floating gate Wilson Current Mirror for Low Power Applications
Madhushankara M and Prashanth Kumar Shetty, Manipal Centre for Information Sciences, Manipal
135
Reverse Engineering By Gate-Level: Fault-Tolerant Combinational Adders
K.C.Pavani and M.Bharathi, Sree Vidyanikethan Engineering College, India
136
Power Aware Physical Design For 3d Chips
Yasmeen Hasan, Integral University, India
137
A Realistically Shaped Three Dimensional Mathematical Model For Temperature Distribution In Multilayered 3d Ic's
Yasmeen Hasan, Integral University, India
139
Super Stack: A Leakage Reduction Technique for 0.5-V Supply Voltage in VLSI Circuits
T. Gowrinath Reddy and K. Suganthi, SRM University, India
141
Universal Crypting-Decrypting Algorithm
Geetesh More, RGPV University, India
142
A Novel Circuit Reduction Technique to Determine the Response of the On-Chip VLSI RC Interconnect for Ramp Input Excitation
Chandan Datta, Madhumanti Datta, Sushmita Sahoo and Rajib Kar, National Institute of Technology, India
149
Design of 8-bit Programmable Crossbar Switch for Network-on-Chip Router
Mohammad Ayoub Khan1 and Abdul Quaiyum Ansari2, 1Ministry of Communications and Information Techology, India and 2Jamia Millia Islamia, India
152
Analysis and Characterization of VCO for UWB Application
Rajesh khatri1 and Neha Maheshwari2, 1S.G.S.I.T.S, India and 2S.V.I.T.S, India
170
Efficient Parallel Multiplier Accumulator Architecture for High Speed Arithmetic
K.Rajesh and K.Nehru, BIT Sathyamangalam, India
171
A Fast Block Matching Algorithm For Motion Estimation Architecture
Shaik Karimullah and Shaik Saheb Basha, MEC, Kadapa
172
CMOS Logic Design with FINFETS Using 32nm TECHNOLOGY
K. Nagarjuna Reddy1, K.V. Ramanaiah1 and K .sudheer2, 1Narayana engineering College, India, 2Narayana Engineering College, India and 3Prakasam Engineering College, India
173
Design And Implementation Of Minimum Value Generator For Ldpc Decoder Design
Aravind P, BannariAmman Institute of Technology, India
174
Implementation of a Digital CMOS Parallel Counter Based on State Look-Ahead Logic
K.Ramesh, Avinash Venigalla and Deepak Kumar Pandey, Srm University, India
175
Energy Management For Energy Harvesting Real Time System With Dynamic Voltage Scaling
Ranvijay1, Rama Shankar Yadav1, Arvind Kumar1 and Smriti Agrawal2, 1Motilal Nehru National Institute of Technology, India and 2Jaypee University of Information Technology, India